Methods and apparatus for improving data transformation in processing devices

ABSTRACT

Methods and apparatus for improving data transformation in image processing device are disclosed. An example apparatus includes a memory, a data writer to write received first data into the memory in a first order, and a data reader to read the first data from the memory in a second order, wherein the data writer is to write second data into the memory in the second order.

RELATED APPLICATION

This patent claims the benefit of U.S. Provisional Patent ApplicationSer. No. 62/508,841, filed May 19, 2017, entitled “METHODS AND APPARATUSFOR BUFFERLESS DATA TRANSFORMATION” and U.S. Provisional PatentApplication Ser. No. 62/510,251, filed May 23, 2017, entitled “METHODSAND APPARATUS FOR BUFFERLESS DATA TRANSFORMATION.” U.S. ProvisionalPatent Application Ser. No. 62/508,841 and U.S. Provisional PatentApplication Ser. No. 62/510,251 are hereby incorporated herein byreference in their entirety.

FIELD OF THE DISCLOSURE

This disclosure relates generally to processing devices, and, moreparticularly, to methods and apparatus for improving data transformationin processing devices.

BACKGROUND

In some electronic systems, data may be sourced in one format butprocessed in another. For example, a camera may output image data in araster/line order but the data may be accessed in another order. Forexample, a processor processing image data using a discrete cosinetransform (DCT) may access the image data in block order.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an example device implemented in accordancewith the disclosure.

FIGS. 2-3 are flow diagrams of an example process that may beimplemented as machine readable instructions that may be executed toimplement the device of FIG. 1.

FIG. 4 illustrates the example state in which data has been written tothe memory in linear order by the data writer of FIG. 1.

FIG. 5 illustrates the example state 500 in which data has been writteninto the memory as the data is read in accordance with read order 402 ofFIG. 4.

FIGS. 6-8 illustrate example executable instructions.

FIG. 9 is a block diagram of an example processor platform that mayexecute the instructions illustrated by FIGS. 2-3 to implement thedevice of FIG. 1.

Wherever possible, the same reference numbers will be used throughoutthe drawing(s) and accompanying written description to refer to the sameor like parts.

DETAILED DESCRIPTION

In some systems for transforming data (e.g., transforming data fromraster/line order storage to block order) a buffer or other memory isutilized as an intermediate storage during the transfer. For example,the data may be read from a source in line order and written to thebuffer in that same order. The data may then be read from the buffer inblock order. During such an operation, the system waits for the data tobe consumed (or nearly completely consumed) before the next batch ofdata can be fetched to avoid overwriting memory that may be waiting tobe read. While double buffering (one buffer for the source data and onebuffer for the application/processing side) can alleviate issues withwaiting for data consumption, such an approach now utilizes two buffers(e.g., more computing resources). Utilizing multiple buffers isparticularly discouraged in embedded computing systems in which the costand physical space needed for implementing a buffer is undesirable.

Methods and apparatus disclosed herein facilitate data transformationthat continues to fill memory (e.g., a single buffer) during the dataread process before all of the memory has been read. In some examples, asingle memory/buffer having a size equal to the product of the number ofrows of the block size and the memory line length may be utilized in thedata transformation process. As disclosed herein, initially, data isread into memory in the order that it is provided by the source. Oncethe memory is filled, the data may be read for processing. As the datais read from memory in the preferred order (e.g., in block order),additional data is written to memory in the order that the memory isread. Accordingly, the data may be accessed in the preferred order andthe data may be refilled into the memory without the need to wait forthe entire memory to be read and/or processed.

FIG. 1 is a block diagram of an example device 100 implemented inaccordance with the disclosure. The example device 100 includes anexample data source 101, an example data receiver 102, an example datawriter 104, an example memory 106, an example data reader 108, and anexample data consumer 110.

The device 100 may be any type of electronic device that handles data.For example, the device 100 may be a computing device, a processingdevice, etc. According to the illustrated example, the device 100 is anembedded computing device.

According to the illustrated example data from the example data source101 is received by the data receiver 102, transferred to the data writer104, and written to the example memory 106 by the data writer 104.During an initial stage, the data writer 104 writes the data to thememory 106 in the order in which the data is provided by the exampledata source 101. For example, when the data source 101 is implemented bya camera that outputs image data that is received by the data receiver102, the example data writer 104 writes the image data to the memory inthe linear order from the camera (e.g., writes the first element (e.g.,block) of data to the first address of the memory 106, writes a secondelement to the second address of the memory, etc.).

According to the illustrated example, data is written to the memory 106until the memory 106 is filled. Once the memory is filled, the data canstart to be read from the memory 106 by the data reader 108. Once thereading begins, a next iteration of writing data to the memory 106 canbegin. In the second and subsequent iterations, elements of data arewritten to the memory locations from which the prior data has been read.For example, after a first element at a first memory address has beenread, the example data writer 104 can write a new element to the firstmemory address. According to the illustrated example, the new data iswritten in the same order that the memory is read. Alternatively, datamay be written to locations in the memory 106 in any order as long asthe data is written to memory locations from which the data reader 108has already read the data. For example, an example write addressincrement process is discussed in conjunction with FIGS. 4 and 5.

The example memory 106 may be any type of memory and/or multiplememories. The example memory 106 is 128 bits of random access memory(RAM) (e.g., 8xFP16 memory). Alternatively, the memory 106 may be anytype volatile and/or non-volatile memory.

The example data reader 108 reads the data from the memory 106 in anorder compatible with the example data consumer 110. For example, thedata that was written to the memory 106 in linear style may be read fromthe memory in a block order to be utilized by the example data consumer110.

The example data consumer 110 may be any operation, mechanism, process,device, etc. that utilizes and/or operates on the data from the memory106. For example, the data consumer 110 may calculate a DCT of the data.According to such an example, the data may be written to the memory 106in the order in which the data is received from the example data source101, but the example data reader 108 reads the data in the block orderutilized in calculating the DCT.

The device 100 may be an Internet of Things (IoT) device. The internetof things (IoT) is a concept in which a large number of computingdevices are interconnected to each other and to the Internet to providefunctionality and data acquisition at very low levels. Thus, as usedherein, an IoT device may include a semiautonomous device performing afunction, such as sensing or control, among others, in communicationwith other IoT devices and a wider network, such as the Internet. IoTdevices are physical objects that may communicate on a network, and mayinclude sensors, actuators, and other input/output components, such asto collect data or perform actions from a real world environment. Forexample, IoT devices may include low-powered devices that are embeddedor attached to everyday things, such as buildings, vehicles, packages,etc., to provide an additional level of artificial sensory perception ofthose things. Recently, IoT devices have become more popular and thusapplications using these devices have proliferated.

Various standards have been proposed to more effectively interconnectand operate IoT devices and IoT network use cases. These include thespecialization of communication standards distributed by groups such asInstitute of Electrical and Electronics Engineers (IEEE), and thespecialization of application interaction architecture and configurationstandards distributed by groups such as the Open Connectivity Foundation(OCF).

Often, IoT devices are limited in memory, size, or functionality,allowing larger numbers to be deployed for a similar cost to smallernumbers of larger devices. However, an IoT device may be a smart phone,laptop, tablet, or PC, or other larger device. Further, an IoT devicemay be a virtual device, such as an application on a smart phone orother computing device. IoT devices may include IoT gateways, used tocouple IoT devices to other IoT devices and to cloud applications, fordata storage, process control, and the like. Such devices may benefitfrom increased efficiency and reduced buffer usage provided inaccordance with the disclosure.

Networks of IoT devices may include commercial and home automationdevices, such as water distribution systems, electric power distributionsystems, pipeline control systems, plant control systems, lightswitches, thermostats, locks, cameras, alarms, motion sensors, and thelike. The IoT devices may be accessible through remote computers,servers, and other systems, for example, to control systems or accessdata.

The example device 100 may be incorporated in a network. The network mayinclude any number of wired and/or wireless devices. For example, thedevice 100 may be connected to and implemented within a cloud network, afog network, a mesh network, a wide area network, a local area network,etc.

While an example manner of implementing the device 100 is illustrated inFIG. 1, one or more of the elements, processes and/or devicesillustrated in FIG. 1 may be combined, divided, re-arranged, omitted,eliminated and/or implemented in any other way. Further, the exampledata source 101, the example data receiver 102, the example data writer104, the example data reader 108, the example data consumer 110 and/or,more generally, the example device 100 may be implemented by hardware,software, firmware and/or any combination of hardware, software and/orfirmware. Thus, for example, any of the example data source 101, theexample data receiver 102, the example data writer 104, the example datareader 108, the example data consumer 110 and/or, more generally, theexample device 100 could be implemented by one or more analog or digitalcircuit(s), logic circuits, programmable processor(s), programmablecontroller(s), graphics processing unit(s) (GPU(s)), digital signalprocessor(s) (DSP(s)), application specific integrated circuit(s)(ASIC(s)), programmable logic device(s) (PLD(s)) and/or fieldprogrammable logic device(s) (FPLD(s)). When reading any of theapparatus or system claims of this patent to cover a purely softwareand/or firmware implementation, at least one of the example, exampledata source 101, the example data receiver 102, the example data writer104, the example data reader 108, and/or the example data consumer 110is/are hereby expressly defined to include a non-transitory computerreadable storage device or storage disk such as a memory, a digitalversatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc.including the software and/or firmware. Further still, the exampledevice 100 may include one or more elements, processes and/or devices inaddition to, or instead of, those illustrated in FIG. 1, and/or mayinclude more than one of any or all of the illustrated elements,processes and devices. As used herein, the phrase “in communication,”including variations thereof, encompasses direct communication and/orindirect communication through one or more intermediary components, anddoes not require direct physical (e.g., wired) communication and/orconstant communication, but rather additionally includes selectivecommunication at periodic intervals, scheduled intervals, aperiodicintervals, and/or one-time events.

Flowcharts representative of example hardware logic, machine readableinstructions, hardware implemented state machines, and/or anycombination thereof for implementing the device 100 are shown in FIGS.2-3. In this example, the machine readable instructions may be anexecutable program or portion of an executable program for execution bya computer processor such as the processor 912 shown in the exampleprocessor platform 900 discussed below in connection with FIG. 9. Theprogram may be embodied in software stored on a non-transitory computerreadable storage medium such as a CD-ROM, a floppy disk, a hard drive, aDVD, a Blu-ray disk, or a memory associated with the processor 912, butthe entire program and/or parts thereof could alternatively be executedby a device other than the processor 912 and/or embodied in firmware ordedicated hardware. Further, although the example program is describedwith reference to the flowchart illustrated in FIGS. 3-4, many othermethods of implementing the example device 100 may alternatively beused. For example, the order of execution of the blocks may be changed,and/or some of the blocks described may be changed, eliminated, orcombined. Additionally or alternatively, any or all of the blocks may beimplemented by one or more hardware circuits (e.g., discrete and/orintegrated analog and/or digital circuitry, an FPGA, an ASIC, acomparator, an operational-amplifier (op-amp), a logic circuit, etc.)structured to perform the corresponding operation without executingsoftware or firmware.

As mentioned above, the example processes of FIGS. 2-3 may beimplemented using executable instructions (e.g., computer and/or machinereadable instructions) stored on a non-transitory computer and/ormachine readable medium such as a hard disk drive, a flash memory, aread-only memory, a compact disk, a digital versatile disk, a cache, arandom-access memory and/or any other storage device or storage disk inwhich information is stored for any duration (e.g., for extended timeperiods, permanently, for brief instances, for temporarily buffering,and/or for caching of the information). As used herein, the termnon-transitory computer readable medium is expressly defined to includeany type of computer readable storage device and/or storage disk and toexclude propagating signals and to exclude transmission media.

“Including” and “comprising” (and all forms and tenses thereof) are usedherein to be open ended terms. Thus, whenever a claim employs any formof “include” or “comprise” (e.g., comprises, includes, comprising,including, having, etc.) as a preamble or within a claim recitation ofany kind, it is to be understood that additional elements, terms, etc.may be present without falling outside the scope of the correspondingclaim or recitation. As used herein, when the phrase “at least” is usedas the transition term in, for example, a preamble of a claim, it isopen-ended in the same manner as the term “comprising” and “including”are open ended. The term “and/or” when used, for example, in a form suchas A, B, and/or C refers to any combination or subset of A, B, C such as(1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) Bwith C, and (7) A with B and with C.

The program of FIGS. 2-3 begins there is data to be handled (e.g.,written into the memory 106 and read out for handling by the exampledata consumer 110). Alternatively, one or more operations may beperformed when data is not ready to be written (e.g., uponinitialization of the example device 100).

The example data writer 104 initializes a write address to zero (block202). The example data reader 108 initializes a read address to zero(block 204). The example data writer 104 initializes a write incrementto 0x1 (e.g., the address increment between consecutive blocks of thememory 106). The example data reader 108 initializes a read increment tobe equal to the number of blocks of the memory (e.g., 0x10).

The example data receiver 102 receives data from the example data source101 (block 210). The example data writer 104 writes the data to thecurrent write address (block 212). The example data receiver 102determines if the memory 106 has been filled (block 214). When thememory 106 has been filled, control proceeds to the operationsillustrated by the flowchart of FIG. 3. When the memory 106 is notfilled, the data writer 104 moves the write address to the next block(e.g., increments the write address by the write increment) (block 216).For example, to ensure that the data writer 104 does not overrun thememory 106, the data writer 104 may increment the write address usingthe formula (write address+write increment) % (memory size−1). Controlthen returns to block 210 to receive and write the new data.

Once the memory 106 has been filled, the example device moves to thenext iteration in which the data reader 108 reads from the memory and,as it does so, the example data writer 104 writes to the memorylocations from which data has already been read. According to theillustrated example, the read process (blocks 302-310) may be performedsubstantially in parallel with the write process (block 320-330). Forexample, each time a block is read from the memory 106, new data may bewritten to the memory location from which the block was read.

To read the data from the memory 106, the example data reader 108 readsfrom the current read address (starting at 0x0 on the first pass) (e.g.,the data reader 108 may read the data from the read address and maytransmit the data to data consumer 110 (block 302). The example datareader 108 determines if all data has been read (block 304). Forexample, the data reader 108 may determine when the read address exceedsthe memory size, may determine when all block locations of the examplememory 106 has been read. When all blocks have not been read, the datareader 108 increments the read address to the next read address locationbased on the read increment (block 306). For example, to ensure that thememory 106 is not overrun, the read address may be increment bycalculating (read address+read increment) % (memory size−1). Controlthen returns to block 302 to read the next memory location.

When all of the memory 106 has been read, the example data reader 108updates the read increment to utilize a read increment that will allowthe data to be read out to the data consumer 110 in the desired blockformat despite the fact that the order of the blocks may no longer bestored in consecutive linear form (block 308). For example, the new readincrement may be set to (write increment×number of blocks) % memory size−1. The example data reader 108 sets the read address to 0x0 (block310).

According to the illustrated example, because the read increment isinitialized to the block size, during the first iteration, the exampledata reader 108 reads the data from the memory 106 in block order eventhough the data has been written to the memory 106 in linear order.

While the example data reader 108 is reading from the memory 106, thedata writer 104 can continue writing to the memory 106 utilizing thememory locations that have already been read out.

The example data writer 104 sets the write address back to 0x0. Theexample, data writer 104 sets the write increment based on the on thecurrent write increment (block 322). While the data writer 104 iswriting to the memory 106 while the data reader 108 is reading from thememory (e.g., but has not finished), the example data writer 104 setsthe write increment to match the increment that the data reader 108 isutilizing to ensure that the data is written to the memory locationsfrom which the data has already been read by the example data reader108. For example, according to the illustrated example, the writeincrement is set using substantially the same calculation as thedetermination of the current read increment. For example, the writeincrement may be set to (write increment×number of blocks) % (memorysize−1).

The example data receiver 102 receives data (block 324). The exampledata writer 104 writes the received data to the memory location at thewrite address (block 326). The example data writer 104 determines if thememory has been filled (e.g., a full iteration of reading the memory andback filling the memory with the next iteration of data) (block 328).When the memory has been filled, control returns to block 320 to startthe next iteration.

When the memory has not been filled (block 328), the data writer 104increments the write address to the next address to be written (block330). For example, the data writer 104 may set the write address to(write address+write increment) % (memory size−1) to ensure that thewrite address does not overrun the memory 106.

Accordingly, the example process of FIGS. 2-3 enables the data to bewritten into memory 106 in a first order and read from the memory 106 ina second order. For example, the data may be written into the memory inlinear order and ready from the memory in block order. Alternatively,the data may be written into memory in block order and read from thememory in linear order.

FIGS. 4-5 illustrate example states 400, 500 of the example memory 106.

FIG. 4 illustrates the example state 400 in which data has been writtento the memory in linear order (e.g., into address 0x0, address 0x1,address 0x2, etc.) by the data writer 104. As illustrated in FIG. 4, thedata reader 108 reads the data in block order 402. For example, the datais read down the first column, down the second column, etc. Accordingly,the use of the modulus operation in the read address incrementing (block306) ensures that the read address wraps from the last element of thefirst column (0x70) to the first element of the second column (0x1).

FIG. 5 illustrates the example state 500 in which data has been writteninto the memory as the data is read in accordance with read order 402 ofFIG. 4. Accordingly, the data is now written in the order proceedingdown the columns. Thus, to read the data in block order, the data isread according to order 502 starting at 0x0 and incrementing by 0x2.

FIGS. 2-5 illustrate an example in which the width of a block can beread at one time. For example, for an 8×8 block size, a read port may beable to read 8 samples at one time. In such an implementation, the blockis accounted for in 8 rows and 1 column is illustrated in FIG. 4 inwhich the block order 402 reads a block by reading the 8 rows of column1.

Other block and memory sizes may be utilized.

In another example, for a block that is N×M, a memory (e.g., a nativebuffer) of size (N×L) elements may be utilized during thetransformation, where L is the line length that is a multiple of M. Forexample, the memory may be sized as N×L elements (e.g., or L/M whenconverting from block order to line order). For such an example, thewrite address may be calculated as illustrated in FIG. 6 and the readaddress may be calculated as illustrated in FIG. 7. As illustrated inthe examples of FIGS. 6 and 7, the divisor for incrementing is theproduct of (the number of blocks times the number of rows of the blocksize times the number of columns of the block size) minus the number ofcolumns of the block size. According to the illustrated examples ofFIGS. 6-7, as data elements are ready from the memory, new data elementsare written to those memory locations to allow the memory to becontinually written to and read without the need for waiting for theentire read process to be completed. Such operation is supported by theuse a matching process for calculating the write address and the readaddress except that the read address increment initially begins at theproduct of the number of blocks times the number of columns in the blocksize to initially read the data out of the memory in block order whilethe data is written in line order starting with an increment of thenumber of columns of the block size during the first write iteration.

While FIGS. 2-7 illustrate an example in which data is transformed fromline order to block order, the methods and apparatus disclosed hereinmay be utilized to perform other transformations (e.g., to transformfrom block order to line order). For example, to switch fromtransforming “line order to block order” to transforming “block order toline order”, the value that the increment is multiplied by changes from“number of blocks” to “N” and the initial read increment changes from“M×number of blocks” (e.g., number of blocks in FIG. 2) to “M×N”. Anexample process for address calculation is illustrated in FIG. 8.

As illustrated in FIG. 8, during the first write iteration, the data isinserted into the memory in the order it is received (e.g., blockorder). Subsequently, the data is read out in line order by, during thefirst iteration, reading the data using the read address increment ofthe product of the number of columns of the block size times the numberof rows of the block size.

FIG. 9 is a block diagram of an example processor platform 900structured to execute the instructions of FIGS. 2-3 to implement thedevice 100 of FIG. 1. The processor platform 900 can be, for example, anembedded device, a server, a personal computer, a workstation, aself-learning machine (e.g., a neural network), a mobile device (e.g., acell phone, a smart phone, a tablet such as an iPad), a personal digitalassistant (PDA), an Internet appliance, a DVD player, a CD player, adigital video recorder, a Blu-ray player, a gaming console, a personalvideo recorder, a set top box, a headset or other wearable device, orany other type of computing device.

The processor platform 900 of the illustrated example includes aprocessor 912. The processor 912 of the illustrated example is hardware.For example, the processor 912 can be implemented by one or moreintegrated circuits, logic circuits, microprocessors, GPUs, DSPs, orcontrollers from any desired family or manufacturer. The hardwareprocessor may be a semiconductor based (e.g., silicon based) device. Inthis example, the processor implements the data receiver 102, the datawriter 104, and the data reader 108.

The processor 912 of the illustrated example includes a local memory 913(e.g., a cache). The processor 912 of the illustrated example is incommunication with a main memory including a volatile memory 914 and anon-volatile memory 916 via a bus 918. The volatile memory 914 may beimplemented by Synchronous Dynamic Random Access Memory (SDRAM), DynamicRandom Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory(RDRAM®) and/or any other type of random access memory device. Thenon-volatile memory 916 may be implemented by flash memory and/or anyother desired type of memory device. Access to the main memory 914, 916is controlled by a memory controller. The example memory 106 may beimplemented by the volatile memory 914 and/or any other memory.

The processor platform 900 of the illustrated example also includes aninterface circuit 920. The interface circuit 920 may be implemented byany type of interface standard, such as an Ethernet interface, auniversal serial bus (USB), a Bluetooth® interface, a near fieldcommunication (NFC) interface, and/or a PCI express interface.

In the illustrated example, one or more input devices 922 are connectedto the interface circuit 920. The input device(s) 922 permit(s) a userto enter data and/or commands into the processor 912. The inputdevice(s) can be implemented by, for example, an audio sensor, amicrophone, a camera (still or video), a keyboard, a button, a mouse, atouchscreen, a track-pad, a trackball, isopoint and/or a voicerecognition system. According to the illustrated example, the datasource 101 is implemented by the input device 922.

One or more output devices 924 are also connected to the interfacecircuit 920 of the illustrated example. The output devices 924 can beimplemented, for example, by display devices (e.g., a light emittingdiode (LED), an organic light emitting diode (OLED), a liquid crystaldisplay, a cathode ray tube display (CRT), an in-place switching (IPS)display, a touchscreen, etc.), a tactile output device, a printer and/orspeaker. The interface circuit 920 of the illustrated example, thus,typically includes a graphics driver card, a graphics driver chip and/ora graphics driver processor. According to the illustrated example, thedata consumer 110 is implemented by the output device 924.

The interface circuit 920 of the illustrated example also includes acommunication device such as a transmitter, a receiver, a transceiver, amodem, a residential gateway, a wireless access point, and/or a networkinterface to facilitate exchange of data with external machines (e.g.,computing devices of any kind) via a network 926. The communication canbe via, for example, an Ethernet connection, a digital subscriber line(DSL) connection, a telephone line connection, a coaxial cable system, asatellite system, a line-of-site wireless system, a cellular telephonesystem, etc.

The processor platform 900 of the illustrated example also includes oneor more mass storage devices 928 for storing software and/or data.Examples of such mass storage devices 928 include floppy disk drives,hard drive disks, compact disk drives, Blu-ray disk drives, redundantarray of independent disks (RAID) systems, and digital versatile disk(DVD) drives.

The machine executable instructions 932 of FIGS. 2-3 may be stored inthe mass storage device 928, in the volatile memory 914, in thenon-volatile memory 916, and/or on a removable non-transitory computerreadable storage medium such as a CD or DVD.

From the foregoing, it will be appreciated that example methods,apparatus and articles of manufacture have been disclosed thatfacilitate data transformation using, in some examples, a singleintermediate buffer. In some examples, improvements are provided tocomputing devices by allowing data to be read and written in the ordercompatible with a particular operation (e.g., receiving linear data forwriting to memory but processing data in block order), allowing for datato be written into the memory as the data is read out without the needto wait for the entire memory to be read, excluding multiple buffers,etc.

Example methods, apparatus, systems and articles of manufacture todetect anomalies in electronic data are disclosed herein. Furtherexamples and combinations thereof include the following.

Example 1 is an apparatus comprising: a memory, a data writer to writereceived first data into the memory in a first order, and a data readerto read the first data from the memory in a second order, wherein thedata writer is to write second data into the memory in the second order.

Example 2 includes the apparatus as defined in example 1, wherein thedata writer is to write the second data into the memory after the datareader has begun reading the first data.

Example 3 includes the apparatus as defined in example 1, wherein thefirst order is linear order and the second order is block order.

Example 4 includes the apparatus as defined in example 1, wherein thedata writer writes the second data in the second order by writing thesecond data in the first order at memory locations based on the secondorder.

Example 5 includes the apparatus as defined in example 1, wherein thedata reader is to read the second data using a read increment determinedbased a) on a write increment used by the data writer to write thesecond data and b) a size of the memory.

Example 6 includes the apparatus as defined in example 1, wherein thedata writer is to write the second data using a second write incrementdetermined based on a) a first increment used in writing the first dataand b) a size of the memory.

Example 7 is a method comprising: writing received first data into amemory in a first order, reading the first data from the memory in asecond order, and writing second data into the memory in the secondorder.

Example 8 includes the method as defined in example 7, furthercomprising writing the second data into the memory after reading thefirst data has begun.

Example 9 includes the method as defined in example 7, wherein the firstorder is linear order and the second order is block order.

Example 10 includes the method as defined in example 7, furthercomprising writing the second data in the second order by writing thesecond data in the first order at memory locations based on the secondorder.

Example 11 includes the method as defined in example 7, furthercomprising reading the second data using a read increment determinedbased a) on a write increment used in writing the second data and b) asize of the memory.

Example 12 includes the method as defined in example 7, furthercomprising writing the second data using a second write incrementdetermined based on a) a first increment used in writing the first dataand b) a size of the memory.

Example 13 is a non-transitory computer readable storage mediumcomprising instructions that, when executed, cause a machine to atleast: write received first data into a memory in a first order, readthe first data from the memory in a second order, and write second datainto the memory in the second order.

Example 14 includes the non-transitory computer readable storage mediumas defined in example 13, wherein the instructions, when executed, causethe machine to write the second data into the memory after reading thefirst data has begun.

Example 15 includes the non-transitory computer readable storage mediumas defined in example 13, wherein the first order is linear order andthe second order is block order.

Example 16 includes the non-transitory computer readable storage mediumas defined in example 13, wherein the instructions, when executed, causethe machine to write the second data in the second order by writing thesecond data in the first order at memory locations based on the secondorder.

Example 17 includes the non-transitory computer readable storage mediumas defined in example 13, wherein the instructions, when executed, causethe machine to read the second data using a read increment determinedbased a) on a write increment used in writing the second data and b) asize of the memory.

Example 18 includes the non-transitory computer readable storage mediumas defined in example 13, wherein the instructions, when executed, causethe machine to write the second data using a second write incrementdetermined based on a) a first increment used in writing the first dataand b) a size of the memory.

Example 19 is an apparatus that includes means for storing data, meansfor writing for writing received first data into the memory in a firstorder, and means for reading the first data from the memory in a secondorder, wherein the means for writing is to write second data into thememory in the second order.

Example 20 includes the apparatus as defined in example 19, wherein themeans for writing is to write the second data into the memory after thedata reader has begun reading the first data.

Example 21 includes the apparatus as defined in example 19, wherein thefirst order is linear order and the second order is block order.

Example 22 includes the apparatus as defined in example 19, wherein themeans for writing is to write the second data in the second order bywriting the second data in the first order at memory locations based onthe second order.

Example 23 includes the apparatus as defined in example 19, wherein themeans for reading is to read the second data using a read incrementdetermined based a) on a write increment used by the means for writingto write the second data and b) a size of the memory.

Example 24 includes the apparatus as defined in example 19, wherein themeans for writing is to write the second data using a second writeincrement determined based on a) a first increment used in writing thefirst data and b) a size of the memory.

Example 25 is a system comprising: an image capture device to captureimage data; an image processing device to: write a first portion of theimage data into a memory in a first order; read the first portion of theimage data from the memory in a second order; transform the firstportion of the image data read from the memory in the second order intotransformed data using a discrete cosine transform; and write a secondportion of the image data into the memory in the second order after thefirst portion of the image data is read from the memory in the secondorder.

Example 26 includes the system as defined in example 25, wherein theimage processing device is to write the second portion of the image datainto the memory after beginning to read the first portion of the imagedata.

Example 27 includes the system as defined in example 25, wherein thefirst order is linear order and the second order is block order.

Example 28 includes the system as defined in example 25, wherein theimage processing device is to write the second portion of the image datain the second order by writing the second portion of the image data inthe first order at memory locations based on the second order.

Example 29 includes the as defined in example 25, wherein the imageprocessing device is to read the second portion of the image data usinga read increment determined based a) on a write increment used by theimage processing device to write the second portion of the image dataand b) a size of the memory.

Example 30 includes the system as defined in example 25, wherein theimage processing device is to write the second portion of the image datausing a second write increment determined based on a) a first incrementused in writing the first portion of the image data and b) a size of thememory.

Although certain example methods, apparatus and articles of manufacturehave been disclosed herein, the scope of coverage of this patent is notlimited thereto. On the contrary, this patent covers all methods,apparatus and articles of manufacture fairly falling within the scope ofthe claims of this patent.

1. An apparatus comprising: a memory; a data writer to write receivedfirst data into the memory in a first order; and a data reader to readthe first data from the memory in a second order, wherein the datawriter is to write second data into the memory in the second order. 2.An apparatus as defined in claim 1, wherein the data writer is to writethe second data into the memory after the data reader has begun readingthe first data.
 3. An apparatus as defined in claim 1, wherein the firstorder is linear order and the second order is block order.
 4. Anapparatus as defined in claim 1, wherein the data writer writes thesecond data in the second order by writing the second data in the firstorder at memory locations based on the second order.
 5. An apparatus asdefined in claim 1, wherein the data reader is to read the second datausing a read increment determined based a) on a write increment used bythe data writer to write the second data and b) a size of the memory. 6.An apparatus as defined in claim 1, wherein the data writer is to writethe second data using a second write increment determined based on a) afirst increment used in writing the first data and b) a size of thememory.
 7. A method comprising: writing received first data into amemory in a first order; reading the first data from the memory in asecond order; and writing second data into the memory in the secondorder.
 8. A method as defined in claim 7, further comprising writing thesecond data into the memory after reading the first data has begun.
 9. Amethod as defined in claim 7, wherein the first order is linear orderand the second order is block order.
 10. A method as defined in claim 7,further comprising writing the second data in the second order bywriting the second data in the first order at memory locations based onthe second order.
 11. A method as defined in claim 7, further comprisingreading the second data using a read increment determined based a) on awrite increment used in writing the second data and b) a size of thememory.
 12. A method as defined in claim 7, further comprising writingthe second data using a second write increment determined based on a) afirst increment used in writing the first data and b) a size of thememory.
 13. A non-transitory computer readable storage medium comprisinginstructions that, when executed, cause a machine to at least: writereceived first data into a memory in a first order; read the first datafrom the memory in a second order; and write second data into the memoryin the second order.
 14. A non-transitory computer readable storagemedium as defined in claim 13, wherein the instructions, when executed,cause the machine to write the second data into the memory after readingthe first data has begun.
 15. A non-transitory computer readable storagemedium as defined in claim 13, wherein the first order is linear orderand the second order is block order.
 16. A non-transitory computerreadable storage medium as defined in claim 13, wherein theinstructions, when executed, cause the machine to write the second datain the second order by writing the second data in the first order atmemory locations based on the second order.
 17. A non-transitorycomputer readable storage medium as defined in claim 13, wherein theinstructions, when executed, cause the machine to read the second datausing a read increment determined based a) on a write increment used inwriting the second data and b) a size of the memory.
 18. Anon-transitory computer readable storage medium as defined in claim 13,wherein the instructions, when executed, cause the machine to write thesecond data using a second write increment determined based on a) afirst increment used in writing the first data and b) a size of thememory.
 19. An apparatus comprising: means for storing data; means forwriting for writing received first data into the memory in a firstorder; and means for reading the first data from the memory in a secondorder, wherein the means for writing is to write second data into thememory in the second order.
 20. An apparatus as defined in claim 19,wherein the means for writing is to write the second data into thememory after the data reader has begun reading the first data. 21-30.(canceled)